Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device comprises a semiconductor substrate, a plurality of capacitors provided above the semiconductor substrate and including a lower electrode, a ferroelectric film, and an upper electrode, and a polysilazane-based coated insulating film provided on the plurality of capacitors and between the plurality of capacitors and burying a gap between the plurality of capacitors.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2003-344651, filed Oct. 2, 2003,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor device including a capacitorusing a ferroelectric film as a capacitor insulating film and a methodof manufacturing the same.

2. Description of the Related Art

FIG. 5 shows a sectional view of a capacitor of a conventionalferroelectric memory. Two capacitors 80 are shown in FIG. 5. Thecapacitor 80 includes a lower electrode 81 and a ferroelectric film 82and an upper electrode 83.

When the ferroelectric film 82 comes into contact with a reducingatmosphere such as hydrogen gas, its electric characteristicsdeteriorate. A large amount of reducing gas is produced in thedownstream process of a semiconductor process. In order to prevent thereducing gas from coming into the capacitor 80 from the outside, thecapacitor 80 is covered with a barrier film 84. Further, the peripheryof the barrier film 84 is completely covered with a silicon dioxide film(TEOS oxide film) 85 formed by a CVD method using tetraethoxysilane(TEOS). In FIG. 5, a reference numeral 86 denotes an insulating film, 87denotes a plug, and 88 denotes a barrier film.

As the degree of integration or fine patterning of a ferroelectricmemory of this kind is increased further, a distance Lcc betweenneighboring capacitors becomes shorter. When the distance Lcc becomesshorter, as shown in FIG. 6, a small gap 89 is produced in a valleybetween the neighboring capacitors 80, whereby the periphery of thecapacitor 80 can not be completely buried with the TEOS oxide film 85.

The reducing gas comes into the TEOS oxide film 85 from the gap 89. Thereducing gas coming into the TEOS oxide film 85 reaches theferroelectric film 82. The reducing gas reaching the ferroelectric film82 causes the deterioration of the electric characteristics of theferroelectric film 82. As a result, this reduces the reliability of theferroelectric memory.

Further, there are also cases where a silicon dioxide film formed by acoating method using a polysiloxane solution is used in place of theTEOS oxide film 85. In this case, since a volume shrinkage ratio whenpolysiloxane changes to silicon dioxide is large, there is produced agap between the barrier film 84 and the silicon dioxide film. This gapcauses the silicon dioxide film to peel off and the electriccharacteristics of the ferroelectric film 82 to be degraded by thereducing gas. Hence, even if the above-described silicon dioxide film isused, the reliability of the ferroelectric memory is reduced.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided asemiconductor device comprising: a semiconductor substrate a pluralityof capacitors provided above the semiconductor substrate and including alower electrode, a ferroelectric film, and an upper electrode; and apolysilazane-based coated insulating film provided on the plurality ofcapacitors and between the plurality of capacitors and burying a gapbetween the plurality of capacitors.

According to an aspect of the present invention, there is provided amethod of manufacturing a semiconductor device comprising: forming afirst conductive film, a ferroelectric film, and a second conductivefilm above a semiconductor substrate in sequence; forming a plurality ofcapacitors by etching the second conductive film, the ferroelectricfilm, and the first conductive film, the plurality of capacitorscomprising a plurality of upper electrodes each including the firstconductive film, the ferroelectric film divided into a plurality ofportions, and a plurality of lower electrodes each including the secondconductive film; and forming a polysilazane-based coated insulating filmon the plurality of capacitors and between the plurality of capacitorsso as to bury a gap between the plurality of capacitors by a coatingmethod using a solution containing polysilazane.

According to another aspect of the present invention, there is provideda method of manufacturing a semiconductor device: forming a plurality oflower electrodes above a semiconductor substrate; forming aferroelectric film and a conductive film in sequence above thesemiconductor substrate so as to cover top surfaces and side surfaces ofthe plurality of lower electrodes; forming a polysilazane-based coatedinsulating film on the conductive film so as to bury a gap between theplurality of lower electrodes by a coating method using a solutioncontaining polysilazane; and forming a plurality of upper electrodes byetching the polysilazane-based coated insulating film and the conductivefilm.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIGS. 1A to 1H are cross sectional views showing a process ofmanufacturing a COP type ferroelectric memory cell according to a firstembodiment of the present invention;

FIGS. 2A to 2E are cross sectional views showing a process ofmanufacturing a three-dimensional COP type ferroelectric memory cellaccording to a second embodiment of the present invention;

FIG. 3 is a cross sectional view showing a modification of thethree-dimensional COP type ferroelectric memory cell of the secondembodiment;

FIGS. 4A to 4B are equivalent circuit and cross sectional view of aseries connected TC unit type ferroelectric RAM;

FIG. 5 is a cross sectional view showing a conventional ferroelectricmemory; and

FIG. 6 is a cross sectional view illustrating a problem with aconventional ferroelectric memory.

DETAILED DESCRIPTION OF THE INVENTION

Hereafter, embodiments of the present invention will be described withreference to the drawings.

FIRST EMBODIMENT

FIGS. 1A to 1G are sectional views to show a process of manufacturing aCOP (capacitor on plug) type ferroelectric memory cell according to afirst embodiment of the present invention.

First, as shown in FIG. 1A, a MOS transistor 2 for switching operationis formed on a silicon substrate 1 by a well-known method. The MOStransistor 2 includes a gate insulating film 3, a gate electrode 4, agate upper insulating film 5, a gate side wall insulating film 6 andsource/drain regions 7.

Next, as shown in FIG. 1B, a silicon oxide film is formed over the wholesurface of the silicon substrate 1 by the CVD method and then thesilicon oxide film is polished by a CMP (chemical mechanical polishing)method to form a silicon oxide film 8 having a flat surface and then acontact hole 9 reaching the source/drain region 7 connected to the lowerelectrode of the capacitor is formed in the silicon oxide film 8.

Next, as shown in FIG. 1C, the side surface and bottom surface of thecontact hole 9 are covered with a barrier metal film 10 and thereafter aplug 11 and a barrier film 12 to prevent the oxidation of the plug 11are formed in the contact hole 9.

The barrier metal film 10 is, for example, a TiN film and the plug 11is, for example, a W plug, and the barrier film 12 is, for example, aTiAlN film, a TiN film, or a TaSiN film.

Next, as shown in FIG. 1D, the first conductive film 13 to be processedinto a plurality of lower electrodes and a ferroelectric film (capacitorinsulting film) 14 are formed and then are subjected to a heatingtreatment to crystallize the ferroelectric film 14.

As the first conductive film 13, for example, a noble metal film such asa Pt film, an Ir film, and a Pd film, or a conductive oxide film such asa SrRuO₃ film and an IrO₂ film, or a laminated film of these films (forexample, Pt film/Ir film) can be used. As a method of forming the firstconductive film 13, for example, a sputtering method or a MOCVD methodcan be used. The first conductive film 13 is formed in a film thicknessof about 100 nm.

As the ferroelectric film 14, for example, a lead titanate zirconate(PZT) film, a strontium bismuth tantalate (SBT) film, a bismuthlanthanum titanate (BLT) film, or a bismuth titanate (BIT) film can beused.

As a method of forming the ferroelectric film 14, the sputtering method,the coating method, or the MOCVD method can be used. In a case where theferroelectric film 14 is formed of a PZT film, a heating treatment tocrystallize the ferroelectric film 14 is performed within a temperaturerange of from 500° C. to 700° C.

Next, as shown in FIG. 1D, the second conductive film 15 to be processedinto a plurality of upper electrodes, a barrier film 16 havingresistance to reduction, and a Silicon oxide film 17 to be processedinto a hard mask are formed in sequence on the ferroelectric film 14 andthereafter a resist pattern 18 is formed on the Silicon oxide film 17.The silicon oxide film 17 is for example a TEOS oxide film.

A film to be used as the second conductive film 15, a method of formingthe second conductive film 15, and a film thickness of the secondconductive film 15 are same as those of the first conductive film 13.

As the barrier film 16, for example, an Al₂O₃ film can be used. As amethod of forming the Al₂O₃ film, for example, a vapor deposition methodcan be used.

As a method of forming the Silicon oxide film 17, for example, a CVDmethod or the coating method can be used.

Next, as shown in FIG. 1E, the Silicon oxide film 17 is etched by usinga resist pattern 18 as a mask. Thereafter, the resist pattern 18 isremoved.

Next, as shown in FIG. 1F, the barrier film 16, the second conductivefilm 15, the ferroelectric film 14, and the first conductive film 13 areetched by a well-known RIE (reactive ion etching) process by using theabove-described etched TEOS oxide film (hard mask) as a mask.

In this manner, a plurality of capacitors 19 can be produced each ofwhich has the lower electrode 13, the ferroelectric film 14, the upperelectrode 15 and the barrier film 16 laminated in sequence and has atapered shape. The shape when viewed from above the upper electrode 15is square or circular and has a side of from about 0.25 μm to 1 μm. Thedistance Lcc between the capacitors ranges from about 0.25 μm to 1 μm.It is acceptable to make the upper electrode and the Lcc larger orsmaller than the above-described values. Thereafter, the hard mask 17 isremoved. A process that the hard mask 17 is not removed can beperformed. In this case, the hard mask 17 is covered with a barrier film20 in the next step.

Next, as shown in FIG. 1G, the barrier film (for example, Al₂O₃ film) 20is formed over the whole surface so as to cover the capacitor 19 andthen a polysilazane film 21 containing a small amount of nitrogen isformed on the barrier film 16 so as to make the surface flat. Theconcentration of nitrogen in the polysilazane film 21 is 10% by weightor less.

In the conventional technology, when the Lcc becomes 1 μm or less, it isdifficult to bury the gap between the capacitors with the TEOS oxidefilm and the gap 89 shown in FIG. 6 is produced in the TEOS oxide film.In particular, when the Lcc becomes 0.5 μm or less, the gap 89 is apt tobe produced in the conventional technology.

However, when the gap between the capacitors is buried with thepolysilazane film 21, even if the Lcc becomes 1 μm or less, inparticular, 0.5 μm or less, the gap 89 shown in FIG. 6 is not produced.That is, according to the present embodiment, the gap produced betweenthe neighboring capacitors can be completely buried with thepolysilazane film 21.

The polysilazane film 21 is formed, for example, in the followingmanner. That is, a polysilazane solution is applied to the surface ofthe silicon substrate 1 by a rotary coating method and the polysilazanesolution applied to the silicon substrate 1 is baked in a nitrogen gasatmosphere at 350° C. for 1 minute and then is subjected to a heattreatment (oxidation heat treatment) in an oxygen gas at a temperaturefrom 550° C. to 700° C. for from 5 minutes to 30 minutes.

The polysilazane solution contains polysilazane (polymer) and carbon aswell, so that the polysilazane film 21 contains carbon. It is clear fromanalysis that the polysilazane film 21 that is one kind of silicondioxide film is different from a silicon dioxide film such as TEOS oxidefilm. As an analysis method, for example, a secondary ion massspectrometry (SIMS) can be used.

In the present embodiment, the oxidation of the plug 11 is prevented bythe barrier film 12, but as described above, the performing of theoxidation heat treatment at low temperatures can effectively prevent theoxidation of the plug 11.

The well-known steps are performed following the step shown in FIG. 1G.That is, as shown in FIG. 1H, a step of forming a via hole connected tothe other source/drain region 7 in the polysilazane film 21 and thesilicon oxide film 8, a step of forming a barrier metal film 22 and aplug 23 in the via hole, and a step of forming a bit line 24electrically connected to the plug 23, and a step of forming a wiring 25which is electrically connected to the upper electrode 15 and to which adriving pulse is applied follow the step shown in FIG. 1G.

In this manner, according to the present embodiment, a ferroelectricmemory can be realized that includes: the plurality of MOS transistors 2provided on the silicon substrate 1; the plurality of capacitors 19provided above the silicon substrate 1 and including the lower electrode13, the ferroelectric film 14 and the upper electrode 15; and thepolysilazane film 21 formed on the plurality of capacitors 19 andbetween the plurality of capacitors 19 and for burying the gap betweenthe neighboring capacitors 19 completely.

In this manner, according to the present embodiment, the gap producedbetween the neighboring capacitors 19 is completely buried with thepolysilazane film 21, so that the deterioration of the ferroelectricfilm 14 by the reducing gas such as hydrogen gas can be prevented, whichresults in improving the reliability of the ferroelectric memory.

SECOND EMBODIMENT

FIGS. 2A to 2E are sectional views to show a process of manufacturing athree-dimensional COP type ferroelectric memory cell according to thesecond embodiment of the present invention. Here, parts corresponding tothose in FIGS. 1A to 1H are denoted by the same reference numerals andtheir detailed descriptions will be omitted.

FIG. 2A shows a sectional view at a stage where the steps up to the stepshown in FIG. 1C of the first embodiment are finished.

Following the step of FIG. 2A, as shown in FIG. 2B, the lower electrode13 is formed so as to be electrically connected to the plug 11 and thenthe ferroelectric film 14 having a thickness of about 100 nm is formedover the whole surface of the lower. electrode 13 so as to cover theside surface and top surface of the lower electrode 13 by the MOCVDmethod and then a heating treatment for crystallizing the ferroelectricfilm 14 is performed.

Next, as shown in FIG. 2B, the second conductive film 15 to be processedinto an upper electrode and has a thickness of about 100 nm is formed onthe ferroelectric film 14 by the MOCVD method and then. the barrier film16 is formed on the second conductive film 15.

While the conductive film described in the first embodiment can be usedas the second conductive film 15, among them, the Ir film or the IrO₂film easily formed by the MOCVD method can be preferably used.

As the barrier film 16, for example, an Al₂O₃ film is used. The filmthickness of the Al₂O₃ film is, for example, 50 nm. An ALD (atomiclayered deposition) method can be preferably used as a method of formingan Al₂O₃ film. This is because the ALD method can easily form thebarrier film 16 having a uniform film thickness on the second conductivefilm 15 having projection portions and depression portions on thesurface.

In the present embodiment, the width W1 of the depression portion isfrom about 0.25 μm to 1 μm and the width W2 (length of one side of asquare) of the projection portion is from about 0.25 μm to 1 μm. Theshape of the projection portion when viewed from above is square orcircular. It is acceptable to make the widths W1 and W2 smaller orlarger than the value described above.

Next, as shown in FIG. 2B, the polysilazane film 21 containing a smallamount of nitrogen is formed on the barrier film 16 so as to make thesurface flat. The concrete method of forming the polysilazane film 21 issuch that has been described in the first embodiment.

Next, as shown in FIG. 2C, a resist pattern 26 having openings above thedepression portions are formed on the polysilazane film 21 and then thepolysilazane film 21, the barrier film 16, the second conductive film 15are etched by using the resist pattern 26 as a mask to separate thesefilms 21, 16 and 15. As a result, a plurality of three-dimensionalcapacitors 27 can be produced.

The well-known steps follow the step in FIG. 2C. That is, as shown inFIG. 2D, a step of forming a barrier film 28, a step of removing theresist pattern 26, a step of forming a polysilazane film 29, and then asis the case with the first embodiment, as shown in FIG. 2E, a step offorming the barrier metal film 22, a step of forming the plug 23, a stepof forming the bit line 24, and a step of forming the wiring 25 followthe step in FIG. 2C.

Here, in the step shown in FIG. 2D, as shown in FIG. 3, it is acceptableto form the barrier film 28 up to a position higher than the barrierfilm 16 exposed to the side wall surface of the opening 30.

In this manner, according to the present embodiment, a ferroelectricmemory can be realized that includes: the plurality of MOS transistors 2formed on the silicon substrate 1; the plurality of capacitors 27 formedabove the silicon substrate 1 and including the lower electrode 13, theferroelectric film 14 and the upper electrode 15; and the polysilazanefilms 21 and 29 formed on the plurality of capacitors 27 and between theplurality of capacitors and for burying the gap between the neighboringcapacitors 19 completely.

Further, also in the present embodiment, because of the same reason asin the first embodiment, the deterioration of the ferroelectric film 14by the reducing gas such as hydrogen gas can be prevented, which resultsin improving the reliability of the ferroelectric memory.

In this regard, the present invention is not limited to theabove-described embodiments but, for example, the present invention canbe applied to a ferroelectric memory (Series connected TC unit typeferroelectric RAM) shown in FIG. 4A. The ferroelectric memory comprisesseries connected memory cell each having a transistor having a sourceterminal and a drain terminal and a ferroelectric capacitor between thetwo terminals. FIG. 4B shows a sectional view of a cell structure shownin FIG. 4A.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A semiconductor device comprising: a semiconductor substrate; aplurality of capacitors provided above the semiconductor substrate andincluding a lower electrode, a ferroelectric film, and an upperelectrode; and a polysilazane-based coated insulating film provided onthe plurality of capacitors and between the plurality of capacitors andburying a gap between the plurality of capacitors.
 2. The semiconductordevice according to claim 1, wherein the polysilazane-based coatedinsulating film contains nitrogen.
 3. The semiconductor device accordingto claim 1, wherein the polysilazane-based coated insulating filmcontains carbon.
 4. The semiconductor device according to claim 1,wherein the plurality of capacitors has a 1 μm or less distance betweenneighboring capacitors.
 5. The semiconductor device according to claim4, wherein the plurality of capacitors has a 0.5 μm or less distancebetween neighboring capacitors.
 6. The semiconductor device according toclaim 1, further comprising a barrier film provided between each of theplurality of capacitors and the polysilazane-based coated insulatingfilm and having resistance to reduction.
 7. The semiconductor deviceaccording to claim 6, wherein the plurality of capacitors has a 0.5 μmor less distance between neighboring capacitors.
 8. The semiconductordevice according to claim 1, wherein the ferroelectric film is providedon a top surface of the lower electrode or a top surface and a sidesurface of the lower electrode.
 9. The semiconductor device according toclaim 1, wherein the capacitor is a capacitor of a ferroelectric memory.10. The semiconductor device according to claim 2, wherein thepolysilazane-based coated insulating film further contains carbon. 11.The semiconductor device according to claim 2, wherein the plurality ofcapacitors has a 1 μm or less distance between neighboring capacitors.12. The semiconductor device according to claim 2, further comprising abarrier film provided between each of the plurality of capacitors andthe polysilazane-based coated insulating film and having resistance toreduction.
 13. The semiconductor device according to claim 2, whereinthe ferroelectric film is provided on a top surface of the lowerelectrode or a top surface and a side surface of the lower electrode.14. The semiconductor device according to claim 2, wherein the capacitoris a capacitor of a ferroelectric memory.
 15. The semiconductor deviceaccording to claim 3, wherein the capacitor is a capacitor of aferroelectric memory.
 16. The semiconductor device according to claim 4,wherein the capacitor is a capacitor of a ferroelectric memory.
 17. Amethod of manufacturing a semiconductor device comprising: forming afirst conductive film, a ferroelectric film, and a second conductivefilm above a semiconductor substrate in sequence; forming a plurality ofcapacitors by etching the second conductive film, the ferroelectricfilm, and the first conductive film, the plurality of capacitorscomprising a plurality of upper electrodes each including the firstconductive film, the ferroelectric film divided into a plurality ofportions, and a plurality of lower electrodes each including the secondconductive film; and forming a polysilazane-based coated insulating filmon the plurality of capacitors and between the plurality of capacitorsso as to bury a gap between the plurality of capacitors by a coatingmethod using a solution containing polysilazane.
 18. The method ofmanufacturing a semiconductor device according to claim 17, furthercomprising: heating the polysilazane-based coated insulating film in anitrogen gas atmosphere after forming the polysilazane-based coatedinsulating film by the coating method.
 19. A method of manufacturing asemiconductor device comprising: forming a plurality of lower electrodesabove a semiconductor substrate; forming a ferroelectric film and aconductive film in sequence above the semiconductor substrate so as tocover top surfaces and side surfaces of the plurality of lowerelectrodes; forming a polysilazane-based coated insulating film on theconductive film so as to bury a gap between the plurality of lowerelectrodes by a coating method using a solution containing polysilazane;and forming a plurality of upper electrodes by etching thepolysilazane-based coated insulating film and the conductive film. 20.The method of manufacturing a semiconductor device according to claim19, further comprising: heating the polysilazane-based coated insulatingfilm in a nitrogen atmosphere after forming the polysilazane-basedcoated insulating film by the coating method.